The present invention relates to a fabrication method for a printed circuit board (PCB), and more particularly to a method of plating a metal layer of the PCB.
PCBs, such as substrates for ball grid array (BGA) packages, generally have exposed pads or fingers for connection to an external device.
In FIG. 1, a top view of an exemplary portion of a PCB for a BGA substrate is shown. Fingers 140 disposed a chip attachment area 120. Trace lines 150 on a top surface respectively extend from fingers 140 to via holes 160 and electrically connect to pads 130 on a bottom surface using trace lines on the bottom surface. A bus line 180, disposed an edge of the PCB, electrically connects to trace lines 150, fingers 140, and pads 130 using branch plating lines 181. The pads 130, fingers 140, trace lines 150, bus line 180, and branch plating lines 181 are typically copper. The pads 130 and fingers 140 are typically exposed for electrical connection to external devices (not shown). The pads 130 and fingers 140 are usually plated with a Ni/Au layer (not shown) by electrical plating where current flows to every pad 130 and finger 140 using bus line 180 and branch plating lines 181 to prevent the exposed pads 130 and fingers 140 from oxidation.
The connections between respective trace lines 150 and bus lines 180 are cut by a step to separate an encapsulated package from the PCB. The branch lines 181, however, remain in the package.
Due to the demand for small-aspect, light and powerful electronic products, PCB design rules demand to layouts with increased density, resulting in increased overall density and reduced pitch in the remained branch lines 181. Thus, a crosstalk effect resulting from mutual inductance and mutual capacitor between the branch lines 181 may not only negatively affect transmission of electrical signals and system stability, but also deviate character impedances of trace lines 150, thereby further negatively affecting the electrical performance of an end product using the PCB.